EIP-8442: 64-bit Opcodes for the EVM
Not every computation needs 256 bits. Counters, offsets, lengths, and the inner loops of hashes and big-number arithmetic fit in 64, and the EVM makes them pay for 256 at every step. This proposal adds twenty-eight instructions that compute on the low 64 bits of their operands: the EVM64 instruction set of EIP-7937 — the same operations at the same costs — encoded as ordinary single-byte opcodes rather than behind a prefix byte. Each is the twin of an existing instruction, at the existing opcode plus 0xC0.
The instructions take no immediate data and enter no mode: they mix freely with the rest of the instruction set, and every result is an ordinary 256-bit word. Alone they make interpreted arithmetic modestly cheaper. Composed with static control flow they compound: code compiled to RISC-V under both executes 19 to 51 times fewer instructions than today’s interpreted EVM, because a stack slot becomes a machine register only when its offset is static and its value fits the register.
Update Log
- 2026-10-14: initial draft
- 2026-10-14: reference implementation
External Reviews
- None as of 2026-10-15
Outstanding Issues
- None as of 2026-10-15